1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, it relates to a semiconductor device which has islands of high voltage and low voltage formed on a single chip and is suitable for effectively enhancing breakdown voltage of the island of high voltage and for extracting a signal used to monitor the potential of the island of high voltage at the island of low voltage, and to a method of manufacturing the same.
2. Description of the Background Art
FIG. 1 is a circuit diagram showing a single phase of a half bridge circuit for driving a load such as a motor. In this figure, insulating gate bipolar transistors (referred to as "IGBT" hereinafter) 1 and 2 are connected in a totem pole manner between a high voltage power source +V and the ground Flywheel diodes 3 and 4 are connected in parallel to IGBTs and 2, respectively. A control circuit is formed on a semiconductor chip 5 to control turning ON/OFF the IGBTs and 2. This control circuit consists of a control logic 6, drive circuits 7 and 8 for producing gate drive signals of the IGBTs 1 and 2 in response to a signal from the control logic 6, and a high breakdown voltage switching element 9 for shifting the level of the signal from the control logic 6 to apply it to the drive circuit 7 on the side of high voltage. The high breakdown voltage switching element 9 is switched into a predetermined manner in response to the signal from the control logic 6 and thereby applies a command from the control logic 6 to the drive circuit 7 on the side of high voltage.
The semiconductor chip 5 includes a low voltage region including the control logic 6 and the drive circuit 8, and a high voltage region including the drive circuit 7 and the high breakdown voltage switching element 9. Conventionally, when the high and low voltage regions are formed on a single chip by means of diffusion isolation, utilizing the diffusion from the surface up to the substrate, regions (islands) 9a and 9b to be isolated are enclosed by a diffusion region 10 of a contrary conductivity type, as shown in FIG. 2. For example, the island 9a may be an island of high voltage, and the island 9b may be an island of low voltage. As it is impractical to perform the diffusion excessuvely deep, the thickness of an epitaxial layer 11 is restricted to be relatively thin, and the high breakdown voltage element must be formed on such a thin island 9a.
U.S. Pat. No. 4292642 discloses the technique. FIG. 3 is a sectional view showing a high breakdown voltage diode disclosed in the USP in which a thin epitaxial layer is employed. A thin n.sup.- epitaxial layer 13 is formed on a p.sup.- substrate 12, and a p.sup.+ diffusion region 14 extending from the surface of the n.sup.- epitaxial layer 13 up to the p.sup.- substrate 12 is provided. On the surface of the n.sup.- epitaxial layer 13, an n.sup.+ diffusion region I5 is provided. An axis R is the ? enter of the rotation, and thus the diode is so structured that the p.sup.+ diffusion region 14 surrounds the n.sup.- epitaxial layer 13 and the n.sup.+ diffusion region 15 to isolate them.
A broken line in the figure shows extension of a depletion layer from the pn junction in case of applying high voltage +V between the p.sup.+ diffusion region 14 and the n.sup.+ diffusion region 15. A graph in the upper portion of the figure shows the intensity of an electric field in the surface, while a graph in the right portion shows the intensity of an electric field corresponding to the depth. Now, the junction between the substrate 12 and the epitaxial layer 13 is named a first pn junction J.sub.1, and the junction between the diffusion region 14 and the epitaxial layer 13 is named second pn junction J.sub.2. Since the first pn junction J.sub.1 is a junction between p.sup.- and n.sup.- regions, a depletion layer extends from the junction to both sides, while since the second pn junction J.sub.2 is a junction between p.sup.+ and n.sup.- regions, a depletion layer extends from the junction merely to one side (to the n.sup.- region). In one-dimensional system, that is, assuming that the first and second pn junctions J.sub.1 and J.sub.2 are infinite plane junctions, the second pn junction J.sub.2 yields only one-second of the breakdown voltage that the first pn junction J.sub.1 does. Thus, the breakdown voltage of the diode is determined based upon that of the second pn junction J.sub.2. However, when the thickness d of the epitaxial layer 13 is small, the extention of the depletion layer from the first pn junction J.sub.1 changes a form of the depletetion layer extending from the second pn junction J.sub.2, and as a result, the depletion layer extends more in the lateral direction (the right direction in the figure) in the surface of the epitaxial layer 13. Consequently, the surface electric field is relieved.
Satisfying the following formula, ##EQU1## the surface electric field is relieved to the same level as the first pn junction J.sub.1 or below, and the breakdown voltage of the diode rises to approximate to the one-dimensional breakdown voltage of the first pn junction J.sub.1. Herein, N denotes an impurity concentration of the n.sup.- epitaxial layer 13, .epsilon. denotes a dielectric constant of the semiconductor material, E is a critical electric field, V.sub.B denotes a breakdown voltage, and L denotes a distance between the p.sup.+ diffusion region 14 and the n.sup.+ diffusion region 15.
The switching element 9 shown in FIG. 1 must have high breakdown voltage. The control logic 6 of the island of low voltage must monitor the potential of the island of high voltage for the protecting operation, as shown by a broken line in the figure. If the high potential of the island of high voltage is inputted as it is to an element of low breakdown voltage in the island of low voltage, the element might be broken, and hence sensing must be done in some indirect way.
This technique is disclosed in "Proceedings of the 1985 International Electron Device Meeting, pp. 37-41, 500 V BIMOS TECHNOLOGY AND ITS APPLICATIONS, Eric J. Wildi et alii". FIG. 4 is a sectional view showing a high breakdown voltage npn transistor having a sense terminal which is disclosed in this thesis. The npn transistor has a structure basically the same as that shown in FIG. 3, and additionally has an n.sup.+ buried region 16 formed in the interface between the p.sup.- substrate 12 and the n.sup.- epitaxial layer 13, an n.sup.+ diffusion region 17 extending from the surface of the n.sup.- epitaxial layer 13 up to the n.sup.+ buried region 16, a p diffusion region 18 formed in the surface of the n.sup.- epitaxial layer 13, and an n.sup.+ diffusion region 19 formed in the surface of the p diffusion region 18. Symbols C, E, B and SEN denote a collector, an emitter, a base and a sense terminal, respectively.
When an applied voltage of a collector terminal C rises, depletion layers in an area X.sub.j extend from the upper and lower side, and hence it works as a JFET. When the area X.sub.j is completely filled with the depletion layer, the potential of the n.sup.+ buried layer 16 and the n.sup.+ diffusion region 17 on the left from the area X.sub.j is separated from the potential of a region on the right of the X.sub.j, and since then, the rising amount of the potential of the collector terminal C is absorbed because of the depletion of the region on the right of the area X.sub.j.
An equivalent circuit to the structure in FIG. 4 is shown in FIG. 5. That is, cascade connection between an npn transistor 20 and a JFET 21 makes a high breakdown voltage npn transistor with a sense terminal. Since the voltage at the sense terminal SEN is expressed by a curve shown in FIG. 6, it is possible to keep the sense voltage low by optimizing the design of the JFET 21. Monitering the sense voltage allows the potential of the region of high voltage (the region on the right of the area X.sub.j) to be sensed indirectly. The sense voltage characteristic can be regulated by altering the length of the area X.sub.j. The region on the right of the area X.sub.j, which is a high voltage keeping region, must be optimized by the technique of the high breakdown voltage diode shown in FIG. 3.
With the structure shown in FIG. 3, it is necessary to satisfy the condition of the formula (1) so as to optimize the breakdown voltage. Especially the requirement of the right half of the formula (I) EQU Nd.ltoreq.5.1.times.10.sup.5 .epsilon.E (2)
requires that the extension of the depletion layer from the first pn junction J.sub.1 sufficiently reaches the surface just before breakdown. Under the optimized condition, the surface electric field takes two peaks with almost the same intensity. Such a surface electric field distribution is unstable depending upon the state of electric charge on the surface, and there arises a problem about the reliability in breakdown voltage.
In addition to that, due to the restriction of the formula (2), the impurity concentration N and the thickness d of the n.sup.- epitaxial layer 13 can not be made so large, and thus the freedom in design is insufficient. As a result, there arises the problems that on state resistance is increased because the impurity concentration of the n.sup.- epitaxial layer 13 can not be made higher and that the breakdown voltage is reduced and leakage current is increased in other islands of low voltage because the thickness d of the n.sup.- epitaxial layer 13 can not be made larger.
On the other hand, with the structure shown in FIG. 4, the sense voltage characteristic is controlled by the length of the area X.sub.j. The length of the area X.sub.j corresponds to the channel length of the JFET, and an element belonging to a class of the breakdown voltage of 500 V requires having a length of 20 .mu.m at the lowest. There is the problem that a large area is required for the structure for sensing, allowing for the existence of the p.sup.+ diffusion region 14 and the n.sup.+ diffusion region 17.
Since the p diffusion region 18 is a base region of a transistor, its size can not be changed as desired. Accordingly, it is necessary to provide the n.sup.+ buried region 16 to regulate the length of the area X.sub.j. It is difficult to form the n.sup.+ buried region 16 and the p diffusion region 18 with the relative position between them kept accurately, and as a result, there arises the problem that the length of the area X.sub.j and accordingly the sense voltage characteristic varies widely.
Further, since the sense voltage characteristic is that the sense voltage rapidly rises until the channel of the JFET is closed and thereafter hardly rises, as shown in FIG. 6, there arises the problem that the voltage change under the condition that the channel of the JFET is closed can not be easily sensed.